Digital/ RTL Design


View: 94

Update day: 19-09-2023

Location: Central

Category: Mechanical / Technical


Salary: 6000 - 8000 SGD / month

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Job content

About Curious Tek

Curious Tek is a leading provider of Total IP solutions for Sensor & Display in mobile storage, automotive connectivity applications.

We are seeking an experienced Digital/RTL Design Engineer to join our growing team in Singapore.

Job Responsibilities:

  • Perform IC design development of SerDes IP products
  • Perform Logic Synthesis, Static Timing Analysis
  • Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
  • Work with Physical designer and RTL designer to achieve timing closure
  • Work with test team in debugging production test issues
  • Help debug & correct any functional issues found in taped-out devices
  • Participate in design reviews, support ISO processes and documentation
  • Work closely with customer’s Systems and Software engineers on FPGA verification


  • Degree/Master in Electrical Electronic Engineering
  • 5 years or above experience in the area of digital IC design
  • Working experience from design to tape-out are essential
  • Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure
  • Experience in using EDA tools from Cadence, Synopsys
  • Knowledge and working experience in one or more of the following:

1. Digital and mixed-signal design

2. USB interface products

3. Graphics processor and driver products

4. Knowledge in connectivity technology such as USB, PCIe, MIPI, SPI, I2C

· Strong Communication skills, high level of independence, self-motivation, and a good team player.

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Deadline: 19-10-2023

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